1. Field of Invention
The present invention relates to an integrated circuit (IC) interconnect process, and more particularly to a method of fabricating a dual damascene structure.
2. Description of Related Art
As the integration degree of semiconductor device is increased, multilevel metal interconnect is used widely. When the resistance of the metal of a metal interconnect is lower, the reliability and the performance of the device are generally higher. Since copper has a relatively low resistance among various metal materials, it is suitably used in a multilevel metal interconnect. However, copper is difficult to etch, so that a Cu-interconnect structure is usually formed with a dual damascene process.
In a dual damascene process, a trench and a via hole are formed in a dielectric layer, and then metal is filled in them to form a metal line and a via plug. FIGS. 1A-1C illustrate a process flow of fabricating a dual damascene structure in the prior art.
Referring to FIG. 1A, a dielectric layer 106 and a silicon nitride (SiN) layer 107 are formed over a substrate 100 with a metal layer 102 and a liner layer 104 thereon. Then, lithography and etching are performed to form, in the SiN layer 107 and the dielectric layer 106, a via hole 108 that exposes a portion of the liner layer 104.
Referring to FIG. 1B, another lithography-etching process is conducted to form in the dielectric layer 106 a trench 110 connected with the via hole 108, and then the portion of the liner layer 104 exposed in the via hole 108 is removed.
Referring to FIG. 1C, a metal material is formed over the substrate 100, filling in the trench 110 and the via hole 108 and covering the SiN layer 107. Then, a chemical mechanical polishing (CMP) step is conducted with the SiN layer 107 as a polishing stop layer to remove the metal material on the SiN layer 107 and form a dual damascene 112.
The above dual damascene process has some problems. Referring to FIGS. 1A-1B, for the liner layer 104 in the via hole 108 is damaged by the etchant in the trench etching, the metal layer 102 is easily exposed degrading the electrical properties. The SiN layer 107 and the dielectric layer 106 are also easily damaged by the etchant in the trench etching so that the top corner of the trench 110 is rounded. Thus, bridging is easily caused between two adjacent dual damascene structures 112, as shown in FIG. 2.